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what are integrated circuits

时间:2021-06-14 01:07:20 来源:网络整理编辑:Knowles Johanson Manufacturing

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BERLIN–The German government has agreed to provide loan guarantees to Advanced Micro Devices Inc.–a move that clears the way for the U.S. chip maker to build a new fab in the eastern city of Dresden, according to a report from Reuters today (November 18, 2003).

BERLIN–The German government has agreed to provide loan guarantees to Advanced Micro Devices Inc.–a move that clears the way for the U.S. chip maker to build a new fab in the eastern city of Dresden, according to a report from Reuters today (November 18, 2003).

Nick Martin, founder and chief executive officer of Altium, said dropping costs, accelerating speeds and rising gate counts for FPGAs are leading inevitably to the devices' integration of most functions traditionally placed on a pc board. That speeds system time-to-market and raises performance while lowering design costs, he said.

But FPGA design to date has required a thorough understanding of an HDL or VHDL, Martin said. With Nexar, Altium aims to bring FPGA to the masses.

what are integrated circuits

It is essentially the same methodology they would use to create a pc board design, but now the platform is an FPGA,” said Martin. We call this the LiveDesign methodology because users can see the results of their design running live on the development board once they have completed it; [they] don't have to wait until the design is physically manufactured.”

The Nexar environment includes hardware design tools, embedded software development tools, presynthesized IP-based components, virtual instrumentation software and a reconfigurable development board that engineers — even those without HDL experience — can use to design and implement an embedded system design in FPGAs.

Like Altium's other board tools, Nexar is a schematic-driven environment, Martin said. Users can pick a target FPGA architecture and then place so-called IP-components — essentially cores that Altium has presynthesized — into the schematic environment, much as they would bring devices into a pc-board schematic environment.

what are integrated circuits

Martin said Altium has developed an extensive library of intellectual-property components, ranging from 8-bit microprocessors to simpler functions. The cores follow the Wishbone interconnect standard adopted by the OpenCores organization to support the design of compatible IP cores.

After functions are placed on an FPGA, an Altium-developed synthesis engine automatically generates glue logic to stitch the functions together.

what are integrated circuits

The Nexar environment also includes a library of IP-based virtual instruments, such as logic analyzers, frequency counters/generators and I/O monitors, that can be incorporated into a design at the schematic level to facilitate system debug. Altium supplies the virtual instruments as presynthesized models.

To perform layout, a user can start by downloading Xilinx Inc.'s or Altera Corp.'s free routing software. The Nexar environment automatically interfaces with the software to direct placement and routing. More-experienced users may wish to purchase the full version of Altera's Quartus or Xilinx's ISE software from those FPGA vendors to perform more-advanced layout, Martin said.

Bandwidth The RapidIO serial and parallel interfaces offer a range of bandwidth options. The 8-/16-bit parallel interface peak bandwidth ranges from 4 to 32 Gbit/s in each direction depending on width and applied clock rate. The 1X/4X serial interface offers a peak bandwidth of 1 to 10 Gbit/s in each direction depending on link speed and lane width.

An early goal for the protocol was to minimize overhead. The parallel interface efficiency ranges from 48 to 87% for data payload sizes between 32 and 256 bytes. Over a similar payload size range, the serial interface efficiency ranges from 53 to 88%, not counting the 8B/10B encoding. These numbers include acknowledgement overhead.

Given that PCI-64 reaches an efficiency of only 49 to 69% over a similar transfer size, there is evidence to suggest the efficiency goal was successfully met—an impressive feat for a system-level packet-oriented protocol.

Ordering, Flows, and Deadlock Avoidance Most transactions in a system do not have specific ordering requirements. However, some operations impose specific ordering requirements. For example, the order of writes to an I/O device or being able to read data updated by a preceding write may be critical to correct operation. Deadlock avoidance is another important case in which ordering in a system is important. Unfortunately, order can impose significant performance limits on a system. For this reason, it is important to provide ordering only when needed and allow system resource the freedom to reorder transactions for performance or quality of service purposes.

For ordering purposes, the concept of flows is defined at the logical layer of the specification. A flow is a sequence of ordered non-maintenance requests between a specific endpoint pair. Request transactions from the same source but targeting different destinations exist in unrelated flows and have no ordering requirements between them. Response transactions are not part of any flow and there is no ordering between them.