GRENOBLE — « Notre nouveau kit de développement Stratix PCI/PCI-X intègre de nouvelles fonctions indiquées par nos clients, permettant aux concepteurs d'accélérer leur cycle de conception et de diminuer les coûts de développement des nouveaux systèmes PCI », déclare Justin Cowling, directeur marketing pour la propriété intellectuelle d'Altera. Annoncée par Altera Corporation, Stratix Edition est la toute première plate-forme de développement FPGA spécialement créée pour la conception de systèmes PCI-W 2.0 Mode. Altera renforce ainsi son engagement dans le standard PCI et agrandit sa gamme de kits de développement PCI pour offrir à ses clients une plus grande flexibilité dans la conception de systèmes PCI.

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HSCM-2GPH2-B1(61)_Datasheet PDF

时间:2021-06-14 00:47:28 来源:网络整理编辑:Wiha

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GRENOBLE — « Notre nouveau kit de développement Stratix PCI/PCI-X intègre de nouvelles fonctions indiquées par nos clients, permettant aux concepteurs d'accélérer leur cycle de conception et de diminuer les coûts de développement des nouveaux systèmes PCI », déclare Justin Cowling, directeur marketing pour la propriété intellectuelle d'Altera. Annoncée par Altera Corporation, Stratix Edition est la toute première plate-forme de développement FPGA spécialement créée pour la conception de systèmes PCI-W 2.0 Mode. Altera renforce ainsi son engagement dans le standard PCI et agrandit sa gamme de kits de développement PCI pour offrir à ses clients une plus grande flexibilité dans la conception de systèmes PCI.

GRENOBLE — « Notre nouveau kit de développement Stratix PCI/PCI-X intègre de nouvelles fonctions indiquées par nos clients, permettant aux concepteurs d'accélérer leur cycle de conception et de diminuer les coûts de développement des nouveaux systèmes PCI », déclare Justin Cowling, directeur marketing pour la propriété intellectuelle d'Altera. Annoncée par Altera Corporation, Stratix Edition est la toute première plate-forme de développement FPGA spécialement créée pour la conception de systèmes PCI-W 2.0 Mode. Altera renforce ainsi son engagement dans le standard PCI et agrandit sa gamme de kits de développement PCI pour offrir à ses clients une plus grande flexibilité dans la conception de systèmes PCI.

The QAM-based designs, however, struggled during the PSD tests, with Metalink failing to get a yes/yes rating on three tests and Infineon failing to receive the rating on 11 tests.

According to the online report from Telcordia, Metalink's problems were primarily the result of unexpected energy in the downstream transmitter. In Infineon's case, the VDSL chip set fell below the lower band notch in the upstream and downstream paths on several instances.

HSCM-2GPH2-B1(61)_Datasheet PDF

According to Telcordia's results, PSD tests on Infineon's chip set were also consistently above the M1-notched template +1 dBm/Hz maximum level” in several instances.

The 16 Mbit/s downstream/1 Mbit upstream and 22 Mbit/s downstream/2 Mbit/s upstream were problem bands for both Metalink and Infineon. Both companies had PSD problems in these bands. These are important configurations for today's carriers,” Sekar said.

Metalink President Francois Crepin did acknowledge that Metalink's chip set encountered some out-of-band problems. This was due to an anti-aliasing filter not working properly. This has nothing to do with QAM or the performance of our device,” Crepin said.

HSCM-2GPH2-B1(61)_Datasheet PDF

Reach tests also appeared to favor DMT. In 16-Mbit down/1-Mbit up configurations, the DMT chip sets reached peak rates of 3,450 feet while the two QAM-based chips delivered a peak reach of 3,000 feet. At 22-Mbit down/3-Mbit up, the DMT chips hit a peak reach of 2,850 feet while the QAM chips delivered a peak reach of 2,550 feet.

Metalink and Infineon disputed claims that QAM struggled in testing and took issue with the test format. Our opinion is that the tests focused only on low-bit-rate services and that these services are not applicable to the Asia Pacific market, which is driving VDSL deployments,” said Mark Tyndall, vice president of business development in Infineon's Wireline Communication Division. Tyndall said valid testing should have been included configurations with 50 Mbit/s downlink speeds and higher.

HSCM-2GPH2-B1(61)_Datasheet PDF

Some of the results that are being quoted are based on optional tests,” Metalink's Crepin said. Some of these tests are influenced by Reed-Solomon coding schemes that are not standardized and are already excluded by the Ethernet in the First Mile standards body.”

If Metalink implemented the non-standard Reed-Solomon coding scheme as well as a constellation providing 1-bit/Hz, known as QAM2, Crepin said the QAM chips sets could achieve up to a 600-foot increase in reach. The new constellation can be added through the addition of firmware to the chip set. Metalink will introduced a version of its chip set in the third quarter that supports the Reed-Solomon coding scheme in question, Crepin added.

When 90 nm starts to take off, however, Sun believes that UMC will get its due. And on 65 nm, he said, the company is deep into its research. Beyond that, teams are looking into everything from low-k and high-k materials to 3-D transistor structures, strained silicon and SOI.

Asked if the company is leaning toward using 157-nm lithography tools or jumping to extreme ultraviolet, as Intel Corp. recently said it would do, Sun demurred, saying this issue is an example of a bleeding-edge” debate. UMC will wait for industry consensus, he said, rather than spend tens of millions on research or soak up time by tweaking immature tools.

It's about manufacturability,” he said. We aren't making a lot of PR efforts. We are coming in, day in and day out, driving R&D for our customers.” In the past six months, progress has accelerated, he said. If you are talking about the real business, the meat, at 90 nm, we have very good yield compared to IBM and we know how our neighbors are doing.”

At 65 nm, Sun said UMC plans a two-phase approach on low-k dielectric materials. The first will see k-values of 2.9 to 2.7, using chemical vapor deposition-based materials it used at 90 nm, such as Novellus' Coral. In phase two, UMC hopes to go below 2.5, also using a CVD material.

UMC is leaning away from a spin-on approach, such as Dow Chemical's SiLK material, which it abandoned more than a year ago, citing issues with the coefficient of thermal expansion.