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1275 SL002_Datasheet PDF

时间:2021-06-14 02:06:13 来源:网络整理编辑:Intel

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It took color TV 50 years to penetrate half the market,” Lipton said. Today people are still digesting high definition. How long this economic downturn goes on will pay a big part” in any short term plans for rolling out 3DTV, he said.

It took color TV 50 years to penetrate half the market,” Lipton said. Today people are still digesting high definition. How long this economic downturn goes on will pay a big part” in any short term plans for rolling out 3DTV, he said.

The narrowband AGC can, be controlled by the baseband, demodulatorvia an analog voltage, (e. g. from a filtered PWM, signal) or by adedicated AGC bus, for faster and disturbance-free, amplitude control.An I2C or a, three-wire-bus is used to control, the IC parameters,whereby two, different modes can be set: one, for best IC linearityperformance, and the other for lowest IC power, consumption.

The choice of which, mode will be used is determined, based onsystem requirements., For example, STB manufacturers, may opt forhigh-linearity setting,, while cellphone manufacturers, would preferthe low-power consumption, setting.

1275 SL002_Datasheet PDF

The reference design includes, a 26MHz crystal for smallest size,and excellent resulting phase, noise. The measured phase noise, isaround -100dBc/Hz @1kHz. It integrates, phase noise power lower, than10mrad leading to a SNR, caused by phase noise of 40dB, and above. Itis also estimated, that this performance would be, sufficient to handlea 256-QAMand, even a 1,024-QAM-OFDM as, planned in the emergingstandard, DVB-T2.

The reference design in Figure 2above could be easily adopted, directly on the PCB of an STB,,USB dongle or any other mobile, devices. The reference design is, basedon a four-layer PCB. Since all, the oscillators are integrated into,the TUA9001, there is little or no, shielding necessary to avoiddisturbances, that observe the basic, EMC rules.

Meeting MBRAI Other reference designs with, TUA9001 are also available for, DVB-T andDVB-H targeting, MBRAI. Due to more stringent, requirements insensitivity and, linearity, the high performance, BGA728L7 LNA has beenused,, where sensitivities of -99dBm will, be achieved.

1275 SL002_Datasheet PDF

Test measurements, done using the BGA728L7 show, sensitivity levelsof -100dBm for, CMMB. The TUA9001 is already, being adopted bycustomers for, mobile phone and portable media, player applications.

For applications using the time, slicing mode, the receiver will be,switched on during the reception, of the desired service only., BothTUA9001 and BGA728L7 or, BFR380 in the reference designs, have thisembedded capability.

1275 SL002_Datasheet PDF

The switching time of TUA9001, and BGA728L7 is below 1ms, while, theBFR380 requires ~1.5ms. One, advantage of using the BGA728L7, is thepossibility to reduce its gain, if the input signal is very high like,in the case of ACI.

First test results, showed the capability of the LNA, able to handlemore than 0dBm, input level in the low-gain mode., Switching its gainfrom low to, high, this LNA achieves the best, of what a RF amplifiercan offer: low noise and high linearity.

Virtex-5 TXT FPGAs tackle the challenges these requirements impose on hardware designers by enabling ultra-high bandwidth communications on a power-optimized programmable platform,” Westman said. This is a critical step forward for the telecommunications industry, and has the potential to accelerate development of the 40-GbE and 100-GbE infrastructure needed to deliver multimedia services.”

The high-bandwidth capabilities of the Virtex-5 TXT platform are also well-suited for high-performance computing and video broadcast applications. The high-transceiver count and ability to support multiple standards on a single programmable device delivers the flexibility, performance and low risk required by these markets.

Like Xilinx' offerings, Achronix' Speedster devices are built using 65-nm processing technology. With the SPD60 (Speedy-60”) as its initial member, the Speedster line uses the Achronix patented picoPIPE acceleration technology designed to speed the way data moves through the FPGA fabric. In the absence of a global clock, picoPIPEs use simple handshake protocols to efficiently control data flow–resulting in significantly improved performance–while using standard RTL for design-entry and employing familiar FPGA tools.

Designers have been lulled into expecting only incremental performance improvements with each new generation of FPGA,” said Achronix CEO John Holt. Our product provides a disruptive leap in performance that opens up new worlds of application design previously unavailable to engineers using FPGAs.”

By coupling this innovative technology with a 10.3-Gbps serializer/deserializer (SerDes) to facilitate high system throughput and integrated DDR2/DDR3 controllers for high-speed memory interface, the Speedster family provides I/O speed to match its core performance.