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时间:2021-06-14 02:25:54 来源:网络整理编辑:Efinix, Inc.

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Most recently, NECX primarily focused on spot market purchases, but had planned to expand its non-contractual buy-sell transaction capability and was building its own portfolio of services through this year's acquisition of the American IC Exchange and Real World Electronics Inc. (see Feb. 22 story).

Most recently, NECX primarily focused on spot market purchases, but had planned to expand its non-contractual buy-sell transaction capability and was building its own portfolio of services through this year's acquisition of the American IC Exchange and Real World Electronics Inc. (see Feb. 22 story).

To ensure this test friendliness and interoperability of cores coming from diverse sources, a standard for embedded core test is under development: IEEE P1500. Although it does not standardize a core's internal test method or an SoC-level test across configuration, it does concentrate on standardizing a core test language capable of expressing all test-related information to be transferred from core provider to core user.

IEEE P1500 also works toward standardizing a configurable and scalable core test wrapper, which allows easy test integration-for example, the test plug-and-play of the core to its host and the next-level core or the SoC. The standard core test wrapper interfaces with an on-chip test access mechanism to deliver the test data during different test modes (internal, external, diagnosis, etc.).

flash memory information

Utilizing embedded test objects, the infrastructure built on-chip and the embedded test database provide scalability and further efficiency in the engineering efforts from silicon debug up to field diagnosis. Moreover, besides simplifying the engineering efforts and reducing the development costs, the use of this embedded system for test and diagnosis, among many other benefits, improves product quality, helps optimize the yield and reduces the manufacturing test costs.

All logic suppliers, driven by the economics of integration, are moving toward system-on-chip (SoC) devices. As the design and mask set costs of these devices skyrocket, however, system OEMs are struggling with the complexities of meeting market demands.

In parallel with this, available time-to-market is shrinking, and the resulting delayed product entry cuts into market share, revenue and profit.

flash memory information

Driven by the convergence of communications, computing and consumer applications, product life cycles are sometimes shrinking to as little as six months. Adversely, SoC design complexity increases the time required to bring competitive products to market, putting a premium on design speed and flexibility.

flash memory information

In this environment, it is no wonder that standard FPGA products are enjoying great success for a number of reasons. FPGAs have always been able to help reduce development cycles, development costs and, thus, time-to-market. Its comparative process disparities with ASICs have been reduced as independent foundries adopt the reprogrammable static-RAM (SRAM) FPGA as a driver for their next-generation technologies. In addition, there has been a rise in the popularity of reconfigurable systems.

Engineers at Actel Corp. have developed a family of embedded, programmable SRAM-based gate array cores used in SoC devices that we are preparing for introduction next year. With this embedded programmable gate array (EPGA), we hope to offer the ASIC and application specific standard product (ASSP) design communities some alternatives.

Altera has unveiled features planned for its next generation of 20-nm products. Extending the promise of silicon convergence, Altera is offering customers a system-integration platform, combining the hardware programmability of FPGAs with the software flexibility of digital signal processors and microprocessors along with the efficiencies of application-specific hard intellectual property (IP). It includes the integration of 40-Gbps transceiver technology, a next-generation variable-precision digital signal processing (DSP) block architecture that delivers over 5 TFLOPs of IEEE 754 floating-point performance, and heterogeneous 3D ICs that integrate FPGAs with a user-customizable HardCopy® ASIC or a variety of other technologies, including memory, third-party ASICs and optical interfaces through an innovative high-speed interface.

Brian Bailey – keeping you covered

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