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WB201-NKR24H_Datasheet PDF

时间:2021-06-14 01:33:31 来源:网络整理编辑:Viega

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To increase verification productivity, the EDA industry came up with a solution similar to what was used to solve the design bottleneck — the concept of abstraction. Higher-level languages such as Verilog and VHDL were introduced to verify chips; these included constructs such as tasks, threading (fork, join) and control structures such as while.” This provided more control to fully exercise the design on all functional corners. However, these constructs were not synthesizable and hence not used by designers as a part of actual design code.

To increase verification productivity, the EDA industry came up with a solution similar to what was used to solve the design bottleneck — the concept of abstraction. Higher-level languages such as Verilog and VHDL were introduced to verify chips; these included constructs such as tasks, threading (fork, join) and control structures such as while.” This provided more control to fully exercise the design on all functional corners. However, these constructs were not synthesizable and hence not used by designers as a part of actual design code.

With energy conservation critical to our 60 million customers and to the overall environment in China, we are dedicated to creating new products that balance energy savings and power minimization while still delivering the highest quality,” he said.

MANHASSET, N.Y. — Sarnoff Corp. has introduced silicon IP aimed at helping TV makers meet a federal requirement that half of all TV sets 36 inches or larger and sold after July 1 must include digital TV capabilities.

WB201-NKR24H_Datasheet PDF

Sarnoff's silicon IP is an integrated audio and video system processor designed to decode and display standard digital TV signals at any resolution that the television set can accommodate, up to and including HDTV.

The digital decoding and display system can decode all 36 input formats specified by the Advanced Television Systems Committee (ATSC) standard. Any input format can be displayed at HDTV resolution (1080i and 720p) or at standard resolution (480p and 480i).

Eventually this system will [also] go into 13-inch TVs,” said Mike Patti, technical director of the Integrated Circuit Systems Group for Sarnoff (Princeton, N.J.). Patti added that the Federal Communications Commission will require TV sets as small as 13 inches to receive digital signals by July 1, 2007, even if they don't have high-definition displays.

WB201-NKR24H_Datasheet PDF

When you look at a digital picture, the difference is obvious compared to an analog TV,” Patti said. He expects the IP solution to generate interest not only from makers of new TVs but also low-cost set-top converter boxes as consumers seek to extend the life of older TV sets.

The display processor can also scale pictures for zoom-in or -out effects.

WB201-NKR24H_Datasheet PDF

The system includes a transport parser, a 24-bit audio decoder, a 32-bit DDR SDRAM controller, a display processor, an on-screen display, a deinterlacer and a digital video encoder. The 24-bit audio decoder subsystem is a DSP solution to decode the Dolby Digital (AC-3) 5.1-channel surround sound often broadcast as part of a digital TV signal.

Sarnoff's digital TV IP is available for immediate delivery. The deliverables include Verilog source code and test benches, firmware, extensive documentation and engineering support. The IP can be customized to add additional features for specific applications.

The challenge until now has been to get the high precision analog functions to work along side the high speed microcontroller core, said Bannatyne. The high resolution SAR converter, has been especially difficult, he noted.

The company is targeting its newest MCUs at applications that require high-speed data acquisition, high accuracy, low noise and low power consumption including applications such as imaging systems, industrial controls, medical and scientific instrumentation, wireless base stations and automatic test equipment. A $24.95 C8051F064 evaluation kit is available to customers that allows for immediate evaluation of the analog performance of on-chip ADCs and evaluation of the software development tools.

With the C8051F064, Silicon Laboratories has enabled a new standard in price and performance by offering a single chip mixed-signal MCU for less than the price of a stand-alone high-speed ADC and separate MCU,” said Derrell Coker, vice president of Silicon Laboratories. Our solution provides designers of embedded applications an affordable programmable solution so they do not have to sacrifice performance for cost or board space.”

The new product family also features in-system debugging that eliminates the need for an emulator and includes features such as single stepping, breakpoints and modifying registers and memory. They are supported with a complete, low cost professional development kit that includes everything required to immediately begin the system design: IDE, target board, cables and power supply.

The C8051F064 evaluation kit is available now for $24.95. The full development kit is available for $299 and provides features typical of in-circuit emulators. The devices are packaged in either a 100-pin TQFP with 59 digital I/O or 64-pin TQFP with 24 digital I/O.