您的当前位置:首页 >HellermannTyton >MIC5219-3.0BMM-TR_Datasheet PDF 正文

MIC5219-3.0BMM-TR_Datasheet PDF

时间:2021-06-14 00:27:10 来源:网络整理编辑:HellermannTyton

核心提示

Get over it. Don't leave your fate in the hands of others.

Get over it. Don't leave your fate in the hands of others.

In order to minimize the effects an inserted card has on live data switching on a backplane, pin staggering should be adopted. Dealing with the input capacitance of the GTLP output is the primary concern. It is the charging of this capacitance that can cause a glitch on the signals present on the backplane. Staggering the card connector pins on a card without VCC BIAS is as follows:

1.GND — establishing the ground connection first provides a path to ground for any unwanted charges that may exist on the card prior to insertion.

MIC5219-3.0BMM-TR_Datasheet PDF

2.I/O Data — connecting data lines second will ensure that I/O pins are high impedance

3.VCC — leaving VCC for the final connection (shortest pin) eliminates the chance of any outputs having a charge prior to insertion.

In the event that pin staggering alone results in bus contention on live insertion, VCC BIAS is a device feature that addresses this problem. This essentially pre-charges the GTLP outputs on the B port to a solid 1V level when voltage is applied to the VCC BIAS pin on the device. Both the VCC BIAS and GND pins must be connected first in order to properly charge the outputs. After the device has power asserted to its VCC pins, the VCC BIAS pre-charge is removed from the B port output pins. This is why the VCC pins must be last to receive power.

MIC5219-3.0BMM-TR_Datasheet PDF

Regardless of the type of pin staggering used (if any) it is very important that the GTLP device being inserted be in high impedance mode, i.e., /OE pins tied high. Inserting the device with either /OEAB or /OEBA directional pins enabled will result in bus contention. Immediately following insertion, the device outputs may be enabled by toggling /OE pins to a low state.

Do You Need Vcc Bias?

MIC5219-3.0BMM-TR_Datasheet PDF

The Fairchild Semiconductor EnSignaTM Lab conducted a study to evaluate and observe the performance of VCC BIAS in a 21-slot backplane. The backplane was configured with a driver in Slot 18 and a receiver in Slot 13 while the remaining slots were left open. Specifications for the backplane include:

VT = 1.5VRT = 35 ohmsVREF = 1VVCC = 3.3VTransceivers: GTLP16T1655's

Based on a low estimate of $10 million in development costs, Colleran said a single 0.13-micron design would have to generate $23 million in sales just to break even.

There are fewer high-volume, high- revenue sockets available today,” he said. That's why we see, along with the drive toward high-speed I/Os, this move toward FPGAs as the solution.”

With a similar vision of the future, rival Xilinx Inc. last week unleashed its Serial Tsunami” initiative to produce by mid-2003 new silicon, IP, and design tools to allow designers to bridge today's parallel I/O designs to next-generation serial I/O. Xilinx currently offers 3.125Gbit/s transceivers in the Virtex-II Pro FPGA family.

Stratix GX takes what Altera learned from its Mercury family–which supports 1.25Gbit/s SerdDes rates–and combines it with a higher-end PLD, Colleran said.

The biggest lesson we learned from Mercury was what to put into hard IP,” he said. This is where Altera will have an advantage over our competitors, who let customers consume general- purpose resources [to do similar functions].”